1. Field of the Invention
The present invention relates to a pulse insertion circuit for inserting pulses used as a frame synchronizing signal, a housekeeping bit or the like, in data multiplexing equipment used in a digital communication system.
2. Description of the Related Art
In digital multiplexing equipment used in a data transmission system, a frame synchronizing signal, a parity bit or the like must be inserted in the data, and a pulse insertion circuit is provided for this purpose. The pulse insertion circuit must operate in response to the data transmission speed, and therefore, when high speed transmission data is processed, the cost of the circuit is high. Accordingly, there is a demand for an economical circuit construction for inserting pulses even when processing high speed transmission data.
In the data transmission system, data of a plurality of channels is often transmitted after multiplexing, and upon reception, is demultiplexed to produce the respective channel data. For example, a transmission system wherein data transmitted at a 45 Mb/s speed is multiplexed by 36 channels and converted to a light signal of 1.6 Gb/s has been proposed.
Essential signals for the digital multiplexing equipment are a frame synchronizing signal, stuff information, housekeeping information as telemetry information, and a variable slot signal for stuffing, or the like. When a multiplexing signal using these signals is formed, because the scale of the circuit operating at a high speed must be reduced, a pulse insertion circuit corresponding to each channel is provided, the frame synchronizing signal and the housekeeping information are inserted in the respective channel data, the stuff bit is inserted to the variable slot, and the multiplexed data in the multiplexing circuit is supplied. Therefore, the pulse insertion circuit is constructed to adapt to an operating speed corresponding to the channel data transmission speed, and the multiplexing circuit is constructed so as to adapt to an operating speed corresponding to the multiplexed data transmission speed.
The pulse insertion circuit in each channel is constituted by a logic IC (integrated circuit) adapted to the data transmission speed. For example, in the case of a transmission speed of less than 40 Mb/s (Mega bit/second), a C-MOS (complementary metal-oxide semiconductor) circuit can be utilized; in the case of a transmission speed of less than 50 Mb/s, a TTL (transistor transistor logic) circuit can be utilized; and in the case of a transmission speed of less than 400 Mb/s, an ECL (emitter-coupled logic) circuit can be utilized.
As mentioned above, in the case of a channel transmission speed of less than 45 Mb/s, since the C-MOS circuit cannot be used, the TTL circuit is used. The electric power consumption of the TTL circuit, however, is about ten times that of the C-MOS circuit, and this constitutes an enormous drawback. In the case of a higher transmission speed, the ECL circuit is utilized, but the power consumption of the ECL circuit is greater than that of the TTL circuit, and therefore, the application of large scale integration techniques becomes difficult. If the ECL circuit is used, a drawback occurs in that a pulse insertion circuit for transmitting data at a speed of more than 400 Mb/s cannot be realized.